Synthesis of Steel-ASIC, a RISC-V Core
Rafael Silva, Vin ́ıcius dos Santos, F ́abio Petkowicz, Rafael Calc ̧ada, Ricardo A. L. Reis · Journal of Integrated Circuits and Systems · 2022
It is presented the design flow of an ASIC version of STEEL, a RISC-V microprocessor developed at UFRGS. The microprocessor core called STEEL implements the RV32I and Zicsr instruction sets of the RISC-V specifications. The whole process entails logical and physical synthesis, using the X-Fab 180 nm, which relies on the Cadence EDA framework. The ASIC circuit operates with a maximum frequency of 19.61 MHz and the estimates obtained from the physical synthesis indicates a power consumption of 10.09 mW.