A 16-bit Adiabatic Reversible Microprocessor
Rene Celis-Cordova, Alexei O. Orlov, John A. Varkey, Jonathan Cowart, James M. Venditto, Bridget Goodwine, Gregory L. Snider, Tien Liu, Jason M. Kulick · ASCEND 2022 · 2022
View Video Presentation: https://doi.org/10.2514/6.2022-4296.vid We present the design and simulation of a 16-bit adiabatic reversible microprocessor implemented in the fully depleted silicon-on-insulator 90 nm technology from Skywater. Adiabatic reversible computing can dramatically reduce the dissipation of circuits by using reversible logic and quasi-adiabatic switching. Reversible logic ensures that information is preserved in a computation. While quasi-adiabatic switching operates circuits slowly relative to their internal RC time constants. Adiabatic CMOS is an immediate implementation of adiabatic reversible computing that uses CMOS circuits with ramping clocks instead of DC power supplies. The adiabatic microprocessor has a 16-bit data-path and implements ten instructions that are enough for universal computation using a MIPS architecture. The processor requires twelve adiabatic ramping clocks to drive the CMOS logic and operates at a maximum frequency of 0.5 GHz. Sequential elements are necessarily non-reversible, but in this design partial energy recovery is performed in the sequential elements using dedicated ramping clocks. A novel energy recovery pad driver is implemented to reduce dissipation when driving external capacitive loads typical in a computing system. The microprocessor was designed using the FDSOI radiation-hardened 90 nm technology from Skywater and verified with high-level simulations.