FPGA Design for Efficient Speech Processing System
Anshu, Ajay Singh Raghuvanshi, Deboraj Muchahary · 2022 2nd Asian Conference on Innovation in Technology (ASIANCON) · 2022
This paper aims,to develop an FPGA design for speech processing using a hardware description language(HDL). The necessary modules used in the implementation of the speech processor are speech pre-processing, feature extraction, and a mixture model.Verilog is the hardware language used for the design process, and then FPGA(Field Programmable Gate Array) is used to reciprocate hardware language into actual hardware. Feature extraction itself is a combination of different blocks, and MFCC(Mel-frequency cepstral coefficients) processor is used to extract feature vectors. The Mixture model is simply a decision-making probabilistic model. GMM(Gaussian Mixture model) is the decision-making block. Xilinx Vivado is the tool for HDL simulation, synthesis, timing analysis. All modules are tested and implemented on the Xilinx Zynq evaluation and development kit FPGA board.