I/O Constraints Optimization using Machine Learning
C Lekshmi, Anmol Khatri, Sourav Saha, Shivangi Gupta, Raj Yadav, Rakshit Bazaz · 2022
Hierarchical designs require high quality I/O constraints for predictable execution for partitions. Complex SOC sub-systems typically take around 10-12 convergence loop to stabilize I/O constraints with evolving collaterals. Proposed solution uses ML capabilities to achieve optimum I/O constraints from the early stages. ML model is trained with features extracted from a top-down timing model alongside delays extracted from implemented database. Cell and RC delays are separately trained and composite I/O budget is ascertained. This approach is successfully deployed in complex SOC sub-systems in sub-7nm and has achieved 30% faster full chip timing convergence with prediction error within 6% of cycle time.