Computation of Real and Complex Valued Signal in Parallel Pipeline FFT Architectures
TJPDM · 2022
Computated valued Fast Fourier Transform introduces an innovative method to estimate through parallel pipelined architectures.The functional frequency of the recommended architecture can be decremented consecutively decrements the power consumption besides the calculation of Real Fast Fourier Transform (RFFT).In this work with these two above mentioned ideas, Complex Valued Fast Fourier Transform (CFFT) and 128 points Radix-2 Real Valued Fast Fourier Transform (RFFT) architectures are developed.FPGA tool such as XILINX SPARTAN -3E, Virtex-4Xc4vfx12 widely utilized experimental device for the execution of multipliers in this work.The proposed work exercise surplus calculation of FFT samples to deplete the hardware complications.Differentiation among recommended and preceding architectures is carried out.75 % of power is reduced in 2 parallel CFFT and RFFT architecture.