High Speed Comparator and Parity generator in QCA based on optimal XOR structure
Trailokya Nath Sasamal, Gaurav Saini, Vineet Jaiswal · 2022
Quantum-dot Cellular Automata (QCA) is emerging as one of the nano-computing technologies that enables significant advantages which are not accessible by current CMOS technology, such as operating frequency (THz), high device density, and ultra low power dissipation. In this work, a low complexity and ultra-high speed QCA comparator and even parity generator is presented employing an optimal XOR gate. The optimal XOR gate is based on cell interaction and non-majority based, which needs fewer cells compared to AND-OR-INVERTER based XOR gates. The proposed comparator requires single layer for its QCA implementation and achieves considerable improvements as compared to prior designs in terms of design metrics like complexity, latency and area usage. To explore the efficacy of non-majority gate based XOR gate, even parity generators of varying lengths 4, 8, 16, and 32bits are also implemented. The proposed designs have superior performance in terms of area, complexity and latency in comparison to existing QCA-based XOR structures. All the proposed designs are implemented, simulated and functionally verified by QCADesigner tool.