Enhancing At-Speed Testability of Complex Inter-Core IO Interfaces
Wilson Pradeep, Muniswara Vorugu, Vevekanenda Gonugunta · 2022
With increased adoption of hierarchical DFT (Design for test) and core based test strategy, there is a great emphasis for effective at-speed testing of inter-core synchronous interfaces. Many design challenges exist which limit efficient usage of functional register reuse based core wrapping to enable it. To address this concern, we propose a novel customized core wrapper cell insertion methodology which allows seamless insertion of functional shared wrapper cells on non-supported sequential endpoints. Experimental results from applying the proposed method on a large hierarchical multi-core design indicate an improvement in shared wrapper cell usage in the range of ~6-8%, which aided in boundary level at-speed transition delay fault coverage increase by ~7.5 to 9% as compared to baseline approach. In cases where usage of shared wrapper cells is entirely infeasible, another alternative method is proposed which uses an overlapped scan configuration scheme to enable at-speed test of delay faults at core boundary. Application of combined test mode in another design showed a gain of 0 to ~92-95% delay fault test coverage improvement at the core boundary.