A Novel, Scalable N*N Reversible Logic Multiplier Design
Akshobhya Jamadagni K R, Sumanth Sakkara, M. Komal · 2022 3rd International Conference on Intelligent Engineering and Management (ICIEM) · 2022
In EDA, Reversible logic has its applications in designing computer graphics, digital signal processing, quantum computing, nanotechnology and cryptography. It is a prospective design style in quantum computing and modern nanotechnology. Although noteworthy proposals have been put forth towards defining new reversible logic gates and sub units of ALUs, design of efficient Multiplier block remains crucial to the realization of a high-performance Reversible Logic ALU that can be leveraged by Deep Neural Networks for high performance MAC operations. This paper proposes the design and comparison of a component scalable Reversible Logic Multiplier using the proposed SAK gate. The verification and simulation have been carried out using Vivado® by Xilinx and further implemented on an Artix®-7 based cost effective FPGA. The proposed design has 27% lesser Gate Count and 12.5% lesser Quantum Cost compared to prior designs.