Design of Area-Power Efficient Parallel Fir Filter with Mux Based Full Adder
Sameena Mohammad, K. Rama Devi · International Journal for Research in Applied Science and Engineering Technology · 2022
Abstract: In this article, here we propose a new architecture of hardware for a high-speed finite impulse response (FIR) filter using seamless fine-grained pipelining. This proposed parallel full pipeline FIR filter can generate an output sample in a limited gate delays by fixing the pipeline registers in between components and also across the components. A precise critical path analysis at the gate level allows to create a suitable pipelining strategy depending on the throughput. This paper also presents modified full adder, based on multiplexers which establishes trade-offs in terms of area, power and delay. The advance FIR filters are incorporate to measure the balance between complexity and speed, and also maximum throughput. The effectiveness of the proposed method is synthesized and simulated using Xilinx Vivado 2018.3 along with improvement of area, delay and power consumption.