CSIP: A Compact Scrypt IP design with single PBKDF2 core for Blockchain mining
Vu Trung Duong Le, Pham Hoai Luan, Thi Hong Tran, Yasuhiko Nakashima · 2022
Developing compact and energy-efficient Scrypt hardware for power-constrained devices is necessary to balance the distribution of blockchain networks. However, existing Scrypt circuits are challenging to achieve in a compact area and energy-efficient since they focus only on maximizing hash performance. Therefore, this paper proposes a Compact Scrypt IP (CSIP) architecture to reduce power consumption while maintaining hashing performance for blockchain mining. Specifically, CSIP uses only one SHA-256 core inside one PBKDF2 core to minimize hardware resources, thus decreasing power consumption significantly. Furthermore, CSIP supports the configuration of parameters to suit the various requirements of blockchain mining. The CSIP design is successfully implemented and verified on a Xilinx Zynq UltraScale+ MPSoC ZCU102 FPGA at a system-on-chip level. Accordingly, the energy efficiency of the CSIP on ZCU102 FPGA is 322 times and 9 times higher than Intel i9-10940X CPU and Nvidia Tesla V100 GPU, respectively. Finally, the experimental results on Xilinx Virtex-7 VC707 FPGA show that the proposed CSIP is significantly better than existing Scrypt architectures in area, power, and energy efficiency.