Power Optimized 7-Port Router Design with BIST Capability for 3D NoC Architecture
WASEEM Shaik Mohammed, Afroz Fatima · DOAJ (DOAJ: Directory of Open Access Journals) · 2017
Three-Dimensional (3D) Network-on-Chip (NoC) architectures being the combination of NoC and 3D die stacking chip integration technology are more prone to faults that might occur with ageing, low supply voltage or physical damage of the chip. Being the heart of NoC, the router is known for consuming significantly high power. With an on-chip testability feature for faults, the amount of power consumed increases linearly with the addition of logical components. This paper, proposes a power optimized Built-In Self-Test (BIST) capable 7-port router architecture for 3D NoC by considering Marching Memory Through Type for buffer design and Cellular Automata Rule 45 for test sequence generation. The power report generated for the proposed design has been compared against that of the conventional router without BIST capability and widely used Linear Feedback Shift Register based BIST capable router architectures and further a constructive discussion in this paper, states the advantages of the proposed design in comparison to its analogues.