Analysis of True Single Phase Clocked Flip-Flop at 180 nm Technology
Webology · 2021
One of the most common as well as an important building block in any digital circuits are the Flip flops.Design is affected by factors such as power, performance, and area.For a systematic design these three must be optimized.When designing within time constraints, throughput and power optimization are the main priorities.Power, Performance and area parameters can be optimized using a plenty of techniques.This study discusses every flip flop design already in use before analysing a 15-transistor, high-speed, low-power flip flop using 180nm technology.To minimize floating internal nodes and reduce dynamic consumption of power, the TSPC FF uses static CMOS and complementary pass transistor circuitry.Flip Flop is implemented using the Cadence Virtuoso tool.Flip Flop's clock frequency is 500MHz, and the supply voltage VDD is 1V.The 180nm technology was utilized in the implementation.