An intelligent verification management approach for efficient VLSI computing system
Konasagar Achyut, Swati K. Kulkarni, Akshata A. Raut, Siba Kumar Panda, Lakshmi Nair · 2022
Any masterpiece is conjoined with all works of engineering, which includes the field of computer science or an electrical and electronics or mixture of both computer and electronics. Today, this gives the industry to understand research, evolve and develop into newer technology unfolding many scriptures behind the engineering works. In the similar manner, this chapter unfolds the prominent works involved in the verification of the designs involved in VLSI domain. Considering machine learning (ML), neural networks and artificial intelligence (AI) concepts and applying these to a wide range of verification approaches are quite interesting. The specific kinds of Register Transfer Level (RTL) design require rigorous verification which is targeted over any type of Field Programmable Gate Array (FPGA) or application-specific integrated circuits (ASICs). The verification process should be closed with testing all possible scenarios that too with intelligent verification methods. This chapter in the following pages brings the unique way of verification procedure involved in the RTL development methodologies using hardware description languages. With the help of system Verilog language, the developed reusable testbench is used for verification. The injected inputs to the testbench are randomized with constraints, such that the design should produce accurate output. To unify the verification language, there is a dedicated methodology commonly known as Universal Verification Methodology (UVM); by this, the chapter is extended to experience the readers also through the coverage-based formal verification. For continuous functional verification, an intelligent regression model is also developed with the help of ML and scripting. With this repeated injection of various test cases is possible in order to verify the functionality. Thus, with the adoption of the presented verification environment and distinctive approach, one can affirm that the design is ready to be deployed over the targeted semiconductor chips. As the verification is an unignorable procedure, this can be used to classify the algorithms developed in ML for data clustering, data encoding and its accurate analysis. More importantly, this chapter allows us to understand an intelligent verification model for testing the design with regression run with the corresponding set-up and the pass/failure analysis steps. This structure may result in a significant reduction of the simulation time for a VLSI verification engineer.