Cache coherency on the S-1 AAP
John Bruner, G. W. Hagensen, E. H. Jensen, J. C. Pattin, Jeff Broughton · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 1987
A cache coherency scheme for shared-memory multiprocessors is described. Unlike most cache coherency schemes, the proposed method does not require the client caches to be connected by a shared bus. Participating caches need only expend cycles to process cache blocks which are shared --- there is no performance penalty for caches which do not contain shared data. The S-1 AAP, a multiprocessor under construction at Lawrence Livermore National Laboratory, uses this scheme. 12 refs., 12 figs.