Hardware Implementation of Network Interface Architecture for RISC-V based NoC-MPSoC Framework
M K Aparna Nair, Police Manoj Kumar Reddy, Y.L. Abijith, Venkatesh Rajagopalan, J. Soumya · 2022
With the increasing number of processing elements or IP cores in a System-on-Chip, Network-on-Chip has become a better solution for on-chip interconnection. RISC-V is an open ISA specification that is strongly growing in the industry as well as academia. In this paper, we have designed and implemented a Network Interface (NI) architecture that can adapt a 32-bit RISC-V core to the on-chip communication framework. The functionality of the design is verified with the behavioral simulations done using Xilinx Vivado software tool. The design is implemented on an FPGA using ZedBoard. The performance parameters of the designed NI architecture are evaluated using Cadence RTL compiler and are found to consume considerably lesser area and power compared with the existing NI architectures in the literature. The behavioural simulations show that the proposed design shows improvement in latency as well compared with the prior work in literature.