Energy Aware Dynamic Load Balancer for Embedded Multi-core Systems
Sachin Ramesh Pundkar, Surajit Pradeep Karmakar, Samir Kumar Mishra, Surendra Kumar Singh, Tushar Vrind · 2022
System on Chip (SoC) for current market requirements have variable workloads, ranging from data & network intensive to CPU-intensive workloads like on-device speech recognition. Managing these workloads on the multiple cores in an optimal manner for both low-latency processing as well as saving power is a big challenge. In this paper, first, we present a Directed Acyclic Graph (DAG) based system model, primarily because messages and events drive most embedded systems by design. Then we present our novel lightweight graph-partitioning algorithm tuned for an embedded platform, through which we partition the tasks into clusters for defining their affinity to specific cores. The algorithm takes care of the execution cost as well as the communication cost of the clusters. Through mathematical model, and verification on Little-Kernel RTOS, we show the proposed DAG-based load balancer reduces the core CPU utilization difference and lowers the power consumption by over 60%, with very low profiling overhead.