Compiler Directives
Slobodan Mijalković · Apress eBooks · 2022
Compiler directives control the preprocessor part of Verilog-A compilation. These directives are capable of performing various transformations on the Verilog-A code but know nothing about the Verilog-A syntax and simply make textual changes as directed. It typically involves the inclusion of the text files, substitution of strings, conditional inclusion or exclusion of code, and setting defaults. The scope of a compiler directive is independent of module definitions and extends from the point where the directive occurs to the next compiler directive that supersedes it.