Hardware Implementation for Determining Perfect and Non-Perfect Square Roots using Dwandwa Yoga on FPGA
Mansi Thakare, Babita Jajodia · 2022 International Conference on Electrical, Computer and Energy Technologies (ICECET) · 2022
This work proposes an efficient and optimized method of binary square root based on Dwandwa Yoga of Ancient Vedic Mathematics feasible for practical and real-time hardware implementations. This work demonstrates the square root of perfect and non-perfect square numbers on the Field Programmable Gate Array (FPGA) platform with an advantage of the reduced combinational delay, low device utilization (no. of slice LUTs) and area-delay product (ADP) over existing state-of-the-art square root architectures. Hardware implementation results of the proposed binary square root architecture are presented for different input-bit lengths (4-bit, 8-bit, and 16bit) on the FPGA platform. Hardware implementation results of 8-bit non-perfect square input with four-bit integer and four-bit fractional bits on Artix7-xc7a350tfbg484-3 FPGA show that the design shows 74.05% reduced no. of Slice LUTs, 46.47% lower combinational delay and 86.109% better area-delay-product (ADP) for the same accuracy with respect to existing reported state-of-the-art literature.