Practical Challenges in Simulating Strong PUFs
Mirunalini Aravindan, J. Kokila · 2022 IEEE IAS Global Conference on Emerging Technologies (GlobConET) · 2022
The ever rising numbers of IoT and smart devices have led to a growing need for security measures and privacy of user’s data. The proposed system puts forth a hybrid PUF involving a 16 bit Anderson PUF and 16 bit Arbiter PUF intended for use in FPGA systems. The proposed system will be implemented on a Zedboard and it allows the user to choose between the PUFs by enabling a switch control. Both Anderson and Arbiter PUFs are delay-based. Anderson PUF utilizes the glitches in the FPGA fabrication to create a unique ‘signature’ for the FPGA. Arbiter PUF employs MUX and uses the time difference between two signals as the unique fingerprint for the device. In this paper, the designing, simulation of the two PUFs using Xilinx and Vivado SDK and the practical difficulties encountered during successful bitstream generation of the same are discussed in detail