Design of Pipeline Acceleration Circuit for Object Tracking Algorithm based on FPGA
Chi Zhang, Zheren Dai, Zhou Li, Rui Han, Yuqi Sun, Xiaocong Wang · 2022 IEEE 4th International Conference on Power, Intelligent Computing and Systems (ICPICS) · 2022
The pipeline acceleration circuit of the improved target tracking algorithm model of the invention can accelerate the target tracking algorithm with higher efficiency and performance, and realize the monitoring, filtering and tracking results of different targets in different pipeline stages at the same time. This method makes full use of FPGA on-chip storage and buffer unit to reduce data on-chip and off-chip access and improve the efficiency of data exchange between pipelines. Each decomposition step of the target tracking algorithm is realized by the FPGA hardware circuit acceleration unit, and different calculation steps are piped and executed in parallel by different circuit modules. The target tracking efficiency is multiple times that of the non piped architecture.