An Architecture of Sparse Length Sum Accelerator in AxDIMM
Shin-haeng Kang, Byeongho Kim, Sukhan Lee, Kyomin Sohn · 2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS) · 2022
In this paper, we have implemented high-efficient near-memory sparse-length sum hardware accelerator which is parallelized over each channel or rank to support Meta's deep learning recommendation model (DLRM). In addition, we described high-level architecture and efforts to enable on the conventional x86 server system. From our suggested near-memory accelerator, we got 1.94 × performance gain on two rank system which are physically multiplied.