NCESPARC+: A Multithreaded SPARC Architecture for the Multiplus Multiprocessor
Júlio Salek Aude, Fábio Rodrigues Martins, Matheus Andrade Barbosa, M. Joao, M. T. Young, S. B. Pinto · 1999
NCESPARC+ is a SPARC V.8 architecture with hardware support to a variable number of thread contexts, which is under development for use within the framework of the Multiplus distributed shared-memory multiprocessor. It is expected to provide an efficient and automatic mechanism to hide the latency of busy-waiting synchronization loops, cache-coherence protocol and remote memory access operations within the Multiplus multiprocessor. NCESPARC+ performs context-switching in at most four processor cycles whenever there is an instruction cache miss, a data dependence in relation to the destination operand of a pending load instruction or a busy-waiting synchronization loop. Results of simulation experiments show the impact of some architectural parameters on the NCESPARC+ processor performance and demonstrate that the use of multiple thread contexts can effectively produce a much better utilization of the processor when long latency operations are performed.