One Bit 8T Full Adder Circuit Using 3T Xor Gate And One Multiplexer
Rathore, Priyanka · Zenodo (CERN European Organization for Nuclear Research) · 2016
ONE BIT 8T FULL ADDER CIRCUIT USING 3T XOR GATE AND ONE MULTIPLEXER ABSTRACT This paper is present very common arithmetic circuit .This circuit is faster has low power consumption by using a new 3 transistor XOR gate. It has two basic features high speed & low power consumption .For the arithmetic circuit very useful parameter low power consumption & time delay. The area of a circuit is directly related to number of gates used in a circuit. In the present design one bit 8T full adder minimizes area, and hence power efficiency. This paper contributes to better understanding of the behavior of single bit full adder cell .When low power delay products are essential full adder cell have been implemented in Tanner 14 Ver. suit and simulation using 70nm CMOS technology to obtain of the performance of the cell with respect to time and power consumption. KEYWORDS Full adder, MOS, multiplexer, power consumption, PDP, time delay & 70nm technology.