Computation-Efficient and Multiplierless Hardware Realization of Decimation in Time FFT
Sampad Chowdhury, Binit Kumar Pandit, Ayan Banerjee · 2022 IEEE Region 10 Symposium (TENSYMP) · 2022
The FFT is one of the critical components for complex digital signal processing (DSP) calculations. The FFTs have a lot of applications like audio and video processing, 5G beamforming, Orthogonal Time Frequency Space Modulation (OTFS), speech and image processing, etc. The time-complexity of FFT poses hindrance to exploit it in real-time applications. Therefore, a fast and hardware-efficient architecture of FFT is needed to be developed for this purpose. This article presents a VLSI architecture design of the Fast Fourier Transform (FFT) algorithm using a multiplier less approach. FFT is an advanced algorithmic form of discrete Fourier transform (DFT), which reduces the number of mathematical calculations. The proposed work involves designing and hardware implementation of an 8 point decimation in time (DIT) Radix 2 FFT processor. The fixed point arithmetic having a datawidth of 8 bit is used for the proposed architecture to reduce the architectural and hardware complexities. The proposed DIT-FFT reduces the computation time due to the use of carry look ahead adders(CLA) in place of ripple carry adders. The proposed VLSI architecture has been implemented on Xilinx's Virtex-7 Evaluation Kit.