FPGA Implementation of Digital Channelizer
Kadir Ayhan, Alptekin Pamuk, Bekir Ahmet Dogrusoz · 2022 30th Signal Processing and Communications Applications Conference (SIU) · 2022
In this paper, designing and implementing process of a device on space-grade FPGA (Field Programmable Gate Array), which channelizes from signals that have 25KHz bandwidth in 30 MHz band around of specific center frequency to band around another specific center frequency, is described detailly. DDS (Direct Digital Synthesis) algorithm, which is used for carrying the signals from wanted frequency to DC is presented. DDS algorithms are presented comparatively in terms of utilization of FPGA resources, and performances. Designed and implemented modules that reduce utilization of FPGA resources, such that; poly-phase filters, CIC (Cascaded Integrator Comb) filters, FIR filters that suppress out of 25KHz, and other signal processing techniques are explained.