Low Power and High-Performance Associative Memory Design
Rohit Lorenzo, Sai Naga Snigdha Vajhala, Mukku Pavan Kumar · 2022 2nd International Conference on Emerging Frontiers in Electrical and Electronic Technologies (ICEFEET) · 2022
Memory is an essential element of every VLSI circuit. This paper reviews Content Addressable Memory (CAM) and its conventional architectures. A model of CAM is proposed using a transmission gate (TG). The new design is proposed with 1-bit storing data. The performance of the proposed design is investigated in terms of the following parameters. power, layout area, power delay product (PDP), and transistors count. The design metrics of the circuit are compared at various technology nodes to understand the working better.