Ultra high speed 802.11n LDPC decoder with seven-stage pipeline in 28 nm CMOS
Łukasz Łopaciński, Alireza Hasani, Goran Panić, Nebojša Maletić, Oliver Schrape, Jesús Gutiérrez, Milos D. Krstic, Eckhard Grass, Rolf Kraemer · 2022 IEEE 95th Vehicular Technology Conference: (VTC2022-Spring) · 2022
This paper reports our latest implementation results of a fully unrolled LDPC decoder prototyped in 28 nm CMOS technology. The decoder achieves 1218 Gbps coded throughput and consumes a 5.49 mm2chip area. The standard min-sum decoding algorithm with four-bit quantization, five unrolled iterations, (648,540) parity matrix, and a seven-stage pipeline is employed. Such implementation achieves a higher data rate than adaptive degeneration and finite-alphabet decoding algorithms, requires less silicon than the solutions mentioned above, and is fully compliant with the IEEE 802.11n WLAN standard.