Exploiting the Common Case When Accelerating Input-Dependent Stream Processing by FPGA
Zhipeng Zhao, Joseph Melber, Siddharth Sahay, Shashank Obla, Eriko Nurvitadhi, James C. Hoe · IEEE Transactions on Computers · 2022
FPGAs have traditionally been successful in accelerating stream processing applications where the amount and type of work performed on each record—e.g., image, packet—do not depend on the record's contents. On the other hand, accelerating ‘input-dependent’ stream processing on FPGAs presents a much more challenging problem where different records in the stream can require widely different operations. It is inefficient and unnecessary to support all operations at the same throughput when the distributions of the operations are skewed. In this paper, we examine the application of the ”make the common case fast” strategy to efficiently accelerate ‘input-dependent’ stream processing on FPGAs. In particular, we study the use offast-slow pathandearly-exittechniques in the design of an FPGA-accelerated network intrusion prevention system (IPS). To avoid overfitting when common-case behavior is varied, we further examinecompile-time re-tuningandruntime adaptationtechniques. A quantitative analysis shows that fast-slow path and early-exit techniques can save an order of magnitude of resources compared to a common-case unaware IPS design. Compile-time re-tuning to specific conditions further achieves 30% – 94% BRAM savings relative to a generalized design. Adding runtime adaptation improves the zero-loss throughput by 1.43 – 2.75 × compared to a fixed design.