The Flexible and Inheritable SMT7 Solution for High-Speed DDR PHY IP with IJTAG
Yichen Xiao, Hao Wu, Xin Sang · 2022 China Semiconductor Technology International Conference (CSTIC) · 2022
The high-speed Double Data Rate Interface intellectual property (DDR PHY IP) integrated into system on chip (SOC) is part of a memory subsystem, supporting the frequency up to 3200Mbps data rate at 1.2V for communication with external memories. To enhance the capabilities of embedded IPs, especially for multiple level architecture, the IEEE P1687 Internal JTAG (IJTAG) is applied. The flexible access is established by the selectable gateway Segment-Insertion-Bit (SIB). Nevertheless, the adjustive scan path signify plenty combinations of SIBs which results in a more complex interface protocol. In this paper, a general solution for DDR PHY validation with IJTAG is presented. Moreover, by testing the packaged products on Automated Test Equipment (ATE) platform, the correlation between traditional design for test (DFT) test and IJTAG protocol-based instruction vector test is accomplished.