Five-Stage Pipelined 32-Bit RISC-V Base Integer Instruction Set Architecture Soft Microprocessor Core in VHDL
Aaron Elson Phangestu, Ir. Totok Mujiono, M.I. Kom, St Ahmad Zaini · 2022
Proprietary technologies with complicated licensing currently dominate the microprocessor industry. As a result, we must seek out a freely available, open-source alternative. In this paper, we discussed the implementation of a five-stage pipelined soft processor core. The core uses the RISC-V RV32I Base Integer Instruction Set Architecture. RISC-V is an open standard ISA that is freely available to use and modify. To implement our processor core, we followed the FPGA design methodology. First, we implemented the design specification with the VHDL Hardware Description Language. Then, siwe mulated the design in the ModelSim simulation environment. Following the verification, we analyzed the resource usage, critical path, and maximum frequency of the processor, then uploaded the processor core to an actual Cyclone IV EP4CE6E22C FPGA. Our CPU core successfully executed all the RV32I instructions, except FENCE, ECALL, and CSR instructions. The proposed processor core runs on 2115 LUTs, 558 flip-flops, and 67,608 memory bits, with a maximum frequency of 62.95 MHz.