High-speed and Low-area Implementations of a Generic and Parallel Integral Image Architecture
Mouhamad Chehaitly, André Lalevée, Thibault Napoléon, Maher Jridi · 2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) · 2022
Nowadays many applications of computer vision and image processing are based on Integral IMage (IIM) algorithm. Since the first use of IIM by Viola-Jones in the face detection algorithm, its computation is still a real challenge and receive a great attention in the research area especially in the field of real time applications. The IIM is greedy in hardware resources where the total number of additions increases with the image size and requires frequent memory accesses which result in the bottleneck effect when realized with CPU. To improve the processing efficiency, we propose a generic parallel/pipeline architectures with and without memory based on dual direction (by columns then by rows) or two levels of data flow oriented in IIM computing architecture. An interesting characteristic of the proposed architectures is the genericity of the calculation, according to the degree of parallelism (the maximum column size and the maximum row size that can be calculated in a clock cycle), the quantization of image values, on the one hand and on the other hand these architectures can be used in two functional modes. Based on the synthesis results of the implementation using Altera Quartus prime lite edition targeting an Intel/Altera Cyclone V - (FPGA), the proposed architecture achieves a high-throughput and low-area, when compared to the state-of-the-art methods. More particularly, for 480 × 640 image size, the proposed IIM architecture involves 765 logic registers, 643 slice LUT, and just 13,7 kbits and it operates at a maximum frequency of 182.28 MHz. These results show that this approach is one of the best candidates for portable applications that require high speed processing and low hardware resources usage.