High-performance Multi-function HMAC-SHA2 FPGA Implementation
Binh Kieu-Do-Nguyen, Trong-Thuc Hoang, Akira Tsukamoto, Kuniyasu Suzaki, Cong‐Kha Pham · 2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) · 2022
Today, Hash-based Message Authentication Code with Secure Hash Algorithm 2 (HMAC-SHA2) is widely used in modern protocols, such as in Internet Protocol Security (IPSec) and Transport Layer Security (TLS). Many authors proposed their HMAC-SHA2 hardware implementations. Some targeted a high-performance design, while others aimed to satisfy an area constraint. Those implementations are acceptable for applications that require only low-cost or high throughput. However, some applications, such as Software-Defined Networking (SDN), Internet-of-Thing (IoT), and Wireless Sensor Network (WSN), need an efficient design that can satisfy both merits. In this paper, an FPGA implementation is proposed that can operate on multiple HMAC-SHA2 variants without re-synthesize. The proposed architecture achieves high performance with a low-cost area. The experimental results show that it can run up to 380-MHz, more than 4.8 Giga-bit-per-second (Gbps), with fewer resources compared to other similar designs.