Power Consumption and Hardware Utilization for Traffic Signs Recognition Models through FPGA Implementation
Prachi Dewan, Vandana Khanna · 2022 International Conference on Machine Learning, Big Data, Cloud and Parallel Computing (COM-IT-CON) · 2022
In this paper, the sequence of MATLAB/Simulink models required for the recognition of the speed-based traffic sign images have been discussed. The resources utilized by all the models along with their dynamic power consumption, when implemented on a Spartan 3E FPGA at 50MHz frequency, have been discussed and compared with the existing literature. Here, the images of traffic signs-30km/h and 50km/h speed limits have been taken. The images have been clicked in real-time environment, with different illumination levels and are of 32 x 32 and 256 x 256 resolution. Four MATLAB/Simulink models for RGB to Gray conversion, Median filtering, Segmentation, and Edge detection have been implemented and the resource utilization as well as the dynamic power consumption of these models have been found using Xilinx ISE EDA platform, when implemented on Spartan 3E hardware. Both the resource utilization and the dynamic power for all the models have been investigated and compared with the existing available literature, to ensure and validate the efficiency and applicability of the present work. The percentage contribution of different models-RGB to Gray, Median filtering, Segmentation, and Edge detection in a total of 156mW dynamic power consumption is found to be 21%, 32%, 2%, and 45%, respectively.