An Analysis of Mapping Polybench Kernels to HPC CGRAs
Markus Weinhardt · 2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) · 2022
This paper presents a detailed analysis of Mapping the Polybench C 4.2.1 kernels to Coarse-Grain Reconfigurable Arrays (CGRAs), targeting High-Performance Computing (HPC). The results show that the Polybench kernels are well suited for acceleration on a CGRA due to their regular array accesses. However, seperately mapping the innermost loops of the Polybench kernels to a CGRA yields only limited speedups because the small size of the generated dataflow graphs limits the available parallelism and results in a low computational intensity. Therefore, loop transformations which will increase the parallelism and the speedups are suggested. While this work focuses on a specific CGRA and its compiler, the observations and conclusions are also transferable to other CGRAs and their compilers.