Toward an Optimal Countermeasure for Cache Side-Channel Attacks
Nivedita Shrivastava, Smruti R. Sarangi · IEEE Embedded Systems Letters · 2022
In the last 15 years, we have witnessed a never-ending arm’s race between the attacker and the defender with respect to cache-based side-channel attacks. We have seen a slew of attacks, countermeasures (CMs), counterattacks, counter-CMs, and so on. We analyze the evolution of this area, propose three necessary conditions for designing a successful CM, and then analyze timing and address-based CMs for popular algorithms, such as AES and PRESENT. We show that an optimal yet trivial solution for timing-based CMs is possible. Furthermore, address-based CMs are inferior to timing-based CMs, and they can be broken in$n^{O(\log (\log (n)))}$time.