High Speed IO Access for Test
Kranthi Kandula, Amit Kapatkar, Hemasagar Babu Reddy · 2022
With the increasing complexity and size of the chips, the test data required to detect faults in SOC is also increasing. Limited number of test pins and test speed pose challenge for running huge test data on SOC. Additionally SoCs are deployed in safety critical applications which require in-system test with a very short test time. Currently there is no solution to drive large set of structural test patterns in in-system. In this paper we present a novel technique High Speed Access Test HSAT to address the above challenges by applying the test patterns through existing High Speed functional interfaces like USB and PCIe on chip both at system level as well as during in-system to deliver data at high bandwidth with minimal pin requirements. The evolution of these protocols to higher speeds provides a scalable solution keeping up with test volume trends.