A 1.1μs 1.56Gb/s/mm2 Cost-Efficient Large-List SCL Polar Decoder Using Fully-Reusable LLR Buffers in 28nm CMOS Technology
Dongyun Kam, Byeong Yong Kong, Youngjoo Lee · 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 2022
This paper presents a cost-efficient large-list SCL polar decoder supporting an ultra-reliable channel coding in 5G and beyond communications. To minimize huge implementation costs, the proposed design utilizes fully-reusable LLR buffers associated with stage unfolding and LLR overwriting schemes, significantly reducing the on-chip buffer overheads by 67% compared to the state-of-the-art decoder. Implemented in a 28nm CMOS, the prototype list-8 decoder achieves 1.1μs and 1.56Gb/s/mm2to decode a 1024b 5G polar codeword while providing the ultra-reliable error-correcting performance.