Deep Learning Hardware Accelerator Unit
Nithish Sindhe, Safdar Ahmed, Aman Rao, Arshiya Anjum · 2022 IEEE 7th International conference for Convergence in Technology (I2CT) · 2022
As Moore's Law slows down, there is increasing interest in the use of hardware accelerators, especially for ML / Big Data workloads. Industrial examples include Google's Tensor Processing Units and the recent Inferentia from Amazon. This design is the DLAU (Deep LearningAccelerator Unit) which is a scalable architecture which employs Deep Learning algorithms (Restricted Boltzmann machine). The Deep Learning Accelerator Unit employs three units that employ tiling techniques. The first block is the Tiled Matrix Multiplication Unit (TMMU), Part Sum Accumulation Unit (PSAU) is the second unit and the last unit is the Activation Function Acceleration Unit (AFAU). These individual units work together as a cohesive unit to enhance the acceleration process, thereby improving computation speeds as the final target of this work.