Exploration on Reusability of Universal Verification Methodology
N. Bhuvaneswary, J. Deny, A. Lakshmi · 2022 2nd International Conference on Advance Computing and Innovative Technologies in Engineering (ICACITE) · 2022
The Universal Verification Approach is a robust verification methodology for a wide range of design sizes and types. The term “universal” refers to the methodology's ability to check everything and everything in the universe - or at least everything in integrated circuits. Through analysis of UVM verification methodology, research is focused on verification reusability. The reuse of the component, platform, test cases, and sequences is reflected in this paper's reusability. Initially the paper discusses about the reusability of UVM platform and test case, followed by a look at a standard UVM verification platform. The I2C protocol is created based on reusable verification environment and the verification results are analyzed.