A novel framework for checking and automating DRC Rules
Jiseong Kim, Sungwook Ahn, KyeungKeun Choe, Ahmed Saleh, Mohamed Al-Imam · 2022
Increasing complexity of the integrated circuits in advanced technologies requires carrying out the physical verification process very efficiently to catch up with the semiconductor market demand. With newer technologies coming out and the number and complexity of design rules increasing, finding ways of reducing the development cycle TAT is critical. One of the challenges that PDK team is constantly faced with is to ensure that each design rule description is correctly interpreted into a DRC code that properly captures the intention of the design rule set by the design rule team. This link between the design rule description and DRC code, if not properly handled, can lead to a reduced DRC deck quality (i.e., more errors), and a longer development cycle. So, creating a flow that automatically and efficiently interprets and checks those rules, with minimum human error, can greatly improve the DRC deck quality. We report the standardized, automated flow which interprets each design rule into a pre-determined category, and with the help of a parameterized library, points to the DRC code that accurately captures the intent of the design rule.