Fast Turn Around Time Development Flow for high Quality LVS rule files
Woonggyu Lee, Seungjae Jung, Bonhyuck Koo, Jongwook Kye, Ahmed Saleh, Ahmed Gharieb, Mohamed Elrefaee, Mohamed Al-Imam · 2022
In the IC design verification flow, LVS (Layout Versus Schematic) is the key step to ensure that a layout design matches accurately with its corresponding schematic design or netlist. As feature size continues to scale down at each new technology node, additional functionalities such as ERC (Electrical Rule Check), LDE (Layout-dependent Effect) parameter extraction and LVS coding for PEX (Parasitic Extraction) are added to the LVS step. The LVS files significantly grow in complexity and consequently both the development and qualification engineering time increases. A delay in LVS readiness from IC foundries directly delays the design process at the design houses and raises the overall cost of product development. This paper describes a novel approach to provide high quality LVS rule files early in the process development phases that minimizes the risks of late redesign spins at the design houses and reduces the cost of IC product development