A Dynamically Configurable Chiplet Testing Technology Based on TAP Controller Architecture
Zhikuang Cai, Yunbo Wang · 2022 IEEE 5th International Conference on Electronics Technology (ICET) · 2022
Aiming at the impact of Chiplet-to-Chiplet testing and the problem of insufficient number of chip ports after integration, the paper proposes a dynamically configurable Chiplet testing technology based on TAP controller architecture (TAP CA). The TAP CA includes TAP state machine controller module, instruction register module and data register module. The TAP state machine controller is used to control the instruction register, and then control and configure the corresponding data register through the instruction register. Finally, the data register is used to control the enable and disable operations of each Chiplet. When the Chiplet is enabled, the Chiplet enters the testing phase. Based on the IEEE 1687 standard, the TAP state machine inside TAP CA is used to realize built-in-self-test. Finally the data value of the configured data register is used to complete the output operation of chip. The above circuit is implemented based on TSMC 40nm process, and the area of TAP CA is only 12085.517 um^2. The ports for the memory testing of the Chiplet are only 5 JTAG ports. The built-in-self-test of all Chiplets can be implemented serially one by one based on TAP CS, and the Chiplet under testing is not affected by other Chiplets.