Analysis, Hardware Specification and Design of a Programmable Performance Monitoring Unit (PPMU) for RISC-V ECUs
Francesco Cosimi, Fabrizio Tronci, Sergio Saponara, Paolo Gai · 2022
The complexity of vehicle applications and the need of reducing the number of processing units are giving great audience to system virtualization. Virtualized architectures with diverse Automotive Safety Integrity Level (ASIL) in the same multicore hardware, known as Mixed Criticality Systems (MCSs), offer flexibility but are extremely challenging in terms of timing validation and resources partitioning. At the same time, RISC- V technologies are becoming central in automotive thanks to open source licensing and customizable solutions. However, most of these architectures cannot sustain MCSs for the absence of features that can be performed only through hardware extensions. In this paper we define details and show a preliminary design and synthesis of a Programmable PMU (PPMU). In virtual systems an extension reporting hardware performance is essential to absolve timing analysis and shared resources balancing purposes. Moreover, in the paper we present a table containing major Hardware Events (HEs) we are interested in, and that can be monitored. The HEs are classified by the role they have in a MCS: Functional Safety (FuSa) analysis or Performance analysis. The synthesis of the PPMU highlighted that the device introduces a limited hardware overhead, e.g. in the worst case the unit uses less than 3 % of available programmable logic of a xczu9eg FPGA device.