DRAM Refresh with Master Wordline Granularity Control of Refresh Intervals
Thomas Vogelsang, Brent Haukness, Eric Linstadt, Torsten Partsch, James Tringali · 2021
DRAM cells need to be periodically refreshed to preserve the charge stored in them. There are multiple mechanisms causing the loss of charge. These mechanisms also vary in strength. The retention time is therefore not the same for all DRAM cells but follows a distribution with multiple orders of magnitude difference between the retention time of cells with the highest charge loss and the cells with the lowest charge loss. Today's DRAM standards have one refresh interval that is set based on the retention time of the weakest cells that are not replaced by redundancy or repaired with ECC. Refresh adds overhead to DRAM energy consumption and command bandwidth and blocks access to banks currently being refreshed. This overhead increases with larger DRAM capacity and shrinking DRAM feature size.