A review on normalization based architecture for floating point numbers
Chepuri Pravalika, Kadi Jaya Ramesh, Rajkumar Sarma · AIP conference proceedings · 2022
In the Present technology, precision plays an important role in many applications like digital signal processing. To represent large or small values, the integer representation of large range is no longer applicable. These values are represented using the IEEE-754 standard based floating-point representation. Floating point processing is used in numerical applications. It is the process of efficiently organizing data in a database. Floating point Normalization is required when two floating point numbers of equal or identical exponents are subtracted, result may become zero and would not satisfy the IEEE floating point format. Normalization should take place in order to make this number compatible with the IEEE format. The Cadence virtuoso tool can be used for designing Normalization process at transistor level. For this design different technologies like 90nm gpdk or tsmc 130nm etc can use. The different possible architectures of Normalization are described based on different parameters.