A 1596-GB/s 48-Gb Stacked Embedded DRAM 384-Core SoC With Hybrid Bonding Integration
Xiping Jiang, Fengguo Zuo, Song Wang, Xiaofeng Zhou, Yubing Wang, Qi Liu, Qiwei Ren, Ming Liu · IEEE Solid-State Circuits Letters · 2022
A 384-Keccak cryptographic cores system on chip (SoC) (die size > 800 mm2and reticle size > 25.5 mm$\times $32.0 mm) with 48-Gb stacked embedded DRAM (SeDRAM) is presented using 110-K/mm2integration density and 0.1-fF capacitive load hybrid bonding integration. The SeDRAM’s advantages of low power and low latency are fully utilized by 49152 wide-IO and network-on-chip design in logic. Thermal stress and reliability are resolved to get a high package yield. The proposed SoC consumes 1596-GB/s bandwidth with 55-W power consumption only and achieves a great system performance improvement.