Efficient ADD/SHIFT architecture for transposed structure of FIR filter using verilog HDL
A. Oruganti, P. Biroju · IET conference proceedings. · 2022
A low-power VLSI system is used to construct the novel filter design that uses the shift and adds a multiplier. The new FIR is similar indirect and translated to the previous FIR models, such as the direct form and earlier shift structure. The implementation is done on the Transposed structural characteristic of FIR since it is beneficial in low power applications. The Smartphone's residual power was determined to be higher at high frequencies. Though its filters are designed to be as power-efficient as possible, different trade-offs are conceivable. The design was superior in terms of reduced power/area. The novel FIR filter is based on the FPGA device and specified using the Xilinx ise/Vivado Design Suite's in-built multiplies and complete adder.