550 Gbps Fully Parallel Fully Unrolled LDPC Decoder in 28 nm CMOS Technology
Alireza Hasani, Łukasz Łopaciński, Goran Panić, Eckhard Grass · 2022
A fully unrolled fully parallel decoding architecture for Low-Density Parity-Check (LDPC) codes is proposed in this paper. Specifically, the iterations of a min-sum decoding scheme are also unrolled and each is implemented with a separate dedicated hardware. The proposed architecture implemented in a 28 nm CMOS technology is able to achieve the throughput of 550 Gbps, occupying an area of 4.98mm2. These results are accomplished with 4-bit quantization of the min-sum decoding messages and six iterations in the case of a (648,540)-LDPC code from IEEE 802.11n. The results show improvements compared with the adaptive degeneration [1] and finite-alphabet [2] decoding algorithms, in terms of both throughput and chip area.