Parallel Computation of Quotients and Partial Remainders to Design Divider Circuits
Hafiz Md. Hasan Babu · 2022
This chapter presents an unprecedented divider circuit by using a new division algorithm. It presents a divider circuit using a new approach of calculating bit difference by using the problem specific heuristic functions to find quotient values. The presented division algorithm is used to constructing the divider circuit calculates the next partial remainder and quotient bits simultaneously. Division is considered as the slowest and most difficult operation among four basic operations in microprocessors. Re-configurable computing has explored a new dimension of computing architecture since its inception in 1960. Re-configurable computing is a computer architecture which combines some of the flexibility of software with the high performance of hardware by processing with a very flexible high speed computing fabrics like field-programmable gate arrays. Modern applications comprise several arithmetic operations, among them addition, multiplication, division, and square root are the frequent ones.