Odin-II Partial Technology Mapping for Yosys Coarse-grained Netlists in VTR
Seyed Alireza Damghani, Kenneth B. Kent · 2022
The Verilog-to-routing (VTR) front-end interface for Verilog compilation, Odin-II, lacks complete support for the Verilog-2005 standard. However, Odin-II provides complex partial mapping for balancing soft logic and hard blocks. Yosys, an open framework for RTL synthesis, provides extensive support for HDLs. However, the Yosys flow forces the user to decide the discrete circuit implementation manually. This research proposes improving device utilization and simplifying the flow by automating complex logic decisions with architecture awareness. According to VTR architectures, hard/soft logic trade-off decisions and heterogeneous logic inference have become available for such coarse-grained BLIF files. Yosys+Odin-II demonstrates promising results by lowering resource consumption, shrinking final circuit footprint, and reducing overall routed wire length, while other criteria remain approximately the same.